Accelerating Deterministic Replay

Deterministic Record and Replay [5, 6, 4] addresses the nondeterministic nature of memory access interleavings in executions of parallel codes. The loss of determinism introduces complexities to common processes such as program analysis or debug of software. This is because two accesses to one location by two processors when at least one of them is writing is a data race. For example, consider a program which has a bug due to insufficient fencing on a TSO machine. Without a fence, the processor is allowed to relax the W → R ordering when advantageous. A common case is that, if the write results in a cache miss, the processor can issue a read before the write completes, i.e. retire from write buffer. This could be a problem, if for example, the write was to acquire a lock. In that situation reads may be issued that return stale data, causing the program to crash. Subsequent executions of the program may or may not exhibit this behavior because their lock write may hit in the cache, the read may not be reordered with the write, or the read may return consistent values when reordered with the write. Deterministic Replay for TSO machines was developed in a previous work by Gilles et al [5]. If a processor is able to record the global processor memory access ordering then a replay system can instrument the code to enforce those orderings. If the processor can capture the complete set of RAW, WAW, and WAR dependencies then it will capture this ordering. Once the orderings are known, then a Causal Precedence Graph (CPG) can be created. The CPG is a Directed Acyclic Graph where the nodes are chunks of a program execution and an edge (A,B) implies that chunk A must occur before chunk B. For our project we focussed on the work done by Gilles et al, as it reflects the state of the art with regards to RnR on TSO machines.